1. Technical Field
The present invention relates generally to a three device BICMOS gain cell for a DRAM memory, and more particularly pertains to a nondestructive read (NDRO) three device gain cell having two FETs and one bipolar device
2. Discussion of the Art
As is well known in the art, DRAMs (dynamic random access memories) are memory devices in which data are stored capacitively, and which must be recharged (refreshed) periodically (every 64 msec or so), or the data will be lost. SRAMs (static random access memories) are memory devices in which static memory cells are generally cross-coupled bistable circuits wherein information is stored by one of the two stable states, such as in a conventional bistable flip-flop, and does not need to be refreshed. Present state of the art DRAMs are relatively dense (16 Mb (megabit) DRAMs in production) as compared with 1 Mb SRAMs, but they have much slower access times than SRAM memories. DRAMS also have much longer cycle times since data is destroyed during a read operation and cell data must be regenerated.
There is a need for DRAMs having improved access times (less latency) as well as improved cycle times. There is also a need for DRAM memories in which the gain cells therein can operate for longer periods of time before a refresh operation is required and which read data in a nondestructive manner, and which require smaller storage capacitance than traditional DRAM cells. There is also a need for larger, higher performance DRAM memories which can be produced commercially at lower costs than are presently available.